Logic converters are used to adapt different logic levels. An input signal is converted in accordance with logic-potential definitions. The function of the converter is to convert the signals with corresponding frequency. Such signals occur, for example, between active components within a chip or between two chips. These components may be close together or far apart. Such components may be linked by a bus, for example. Another application is if the components are incorporated in network elements which are far apart.
Signal-exchanging systems or generally telecommunications systems and networks are designed to exchange (electric) signals reliably, without errors, and as fast as possible. This is accomplished by using defined uniform transmission rates (frequencies) and defined amplitudes, for example.
Differential emitter-coupled logic (ECL) circuitry is often used in high-speed data transmission applications because of its higher speed of operation and its advantageous signal characteristics. The differential aspect of these low-level signals provides a good signal-to-noise ratio, for example.
It is technologically possible and desirable to convert low-level ECL signals to signals of higher levels, such as those of complementary metal oxide semiconductor (CMOS) logic circuits, without a significant degradation in speed, so that such a converter can drive CMOS circuits.
Known ECL to CMOS converters make the conversion at the expense of speed and/or drive capability. ECL can be switched faster than CMOS, but attempts to speed up the conversion process often diminish the output drive capability of the circuit. Circuits with this disadvantage are described in U.S. Pat. No. 5,726,588 or U.S. Pat. No. 5,426,381.
The conversion of ECL signals to CMOS signals is commonly performed in three stages. An input stage receives and buffers the ECL signals, which are applied with a voltage swing of a few 100 mV referenced to the positive supply voltage. A level shifter stage shifts the ECL levels in the direction of the CMOS switching threshold and increases the voltage swing, and an output stage forms the CMOS-compatible output signal.
The invention starts from a converter circuit which does not have the above-described disadvantage. This converter circuit is disclosed in U.S. Pat. No. 6,252,421 and shown in FIG. 1.
This circuit has the following drawbacks. The level shifter is a bipolar differential stage 20, . . . , 24 whose output signals are used to drive CMOS inverters 25, . . . , 28 and 37, . . . , 40. If this arrangement is operated on low supply voltages, e.g., below 3 volts, the output level for the low state can no longer reach the CMOS switching level, which is usually one half the supply voltage.
This is due to the circuit technology used for the level shifter 20, . . . , 24. The differential stage 20, . . . , 23 requires a current source 24 across which a voltage drop of typically 0.8 V is developed. The voltage drop across the switching transistors 22, 23 of differential stage 20, . . . , 23 corresponds to the on-state voltage, typically also approximately 0.8 V. Because of the saturation effect, the collector potential must not fall below the base potential, i.e., the output level for the low state cannot decrease below 1.6 V. Accordingly, the CMOS switching threshold must be above 1.6 V. This gives a minimum possible supply voltage of approximately 1.6V·2=3.2V.
By means of an unbalanced design of the inverters 25, . . . , 28 and 37, . . . , 40, which are driven by the differential stage 20, . . . , 23, this voltage can be slightly reduced. However, the unbalanced inverters result in longer switching times.
Another disadvantage of the prior-art solutions is that the level shifter 20, . . . , 24 has a relatively large voltage swing, since the bipolar differential stage 20 . . . , 23 switches from the minimum level for the low state to the level of the supply voltage for the high state. The large voltage swing results in relatively long switching times.